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fod0721, FOD0720, fod0710 ?high cmr, 25mbit/sec logic gate optocoupler ?004 fairchild semiconductor corporation www.fairchildsemi.com fod0721, FOD0720, fod0710 rev. 1.0.8 april 2009 fod0721, FOD0720, fod0710 high cmr, 25mbit/sec logic gate optocoupler features 20kv/? minimum cmr 40ns max. propagation delay data rate, non-return zero coding ? 25mbit/sec (fod0721 and FOD0720) ? 12.5mbit/sec (fod0710) pulse width distortion ? 6ns (fod0721) ? 8ns (FOD0720 and fod0710) +5v cmos compatibility extended industrial temperate range ? -40 to 100? temperature range safety and regulatory approvals ? ul1577, 3750 vacrms for 1 min. (file #e90700, volume 2) ? iec60747-5-2 pending approval applications industrial ?ldbus communications ? profibus, devicenet, can, rs485 programmable logic control isolated data acquisition system description the fod0721/0720/0710 family utilizes fairchild? patented coplanar packaging technology, optoplanar , and optimized ic design to guarantee minimum 20kv/? common mode noise rejection (cmr) rating. these high-speed logic gate optocouplers consist of a high-speed algaas led driven by a cmos ic coupled to a cmos detector ic, comprising an integrated photo- diode, a high-speed transimpedance amplifier and a voltage comparator with an output driver. the cmos technology coupled to the high efficiency of the led achieves low power consumption as well as very high speed (40ns propagation delay, 6ns pulse width distortion). these devices are available in a compact 8-pin small outline package. functional schematic 1 2 3 4 5 6 7 8 v dd2 v i h l v o h l led off on nc v o gnd2 tr uth table *: pin 3 must be left unconnected v dd1 v i * gnd1
?004 fairchild semiconductor corporation www.fairchildsemi.com fod0721, FOD0720, fod0710 rev. 1.0.8 2 fod0721, FOD0720, fod0710 ?high cmr, 25mbit/sec logic gate optocoupler pin definitions absolute maximum ratings (t a = 25? unless otherwise speci?d.) stresses exceeding the absolute maximum ratings may damage the device. the device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. in addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. the absolute maximum ratings are stress ratings only. recommended operating conditions the recommended operating conditions table defines the conditions for actual device operation. recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. fairchild does not recommend exceeding them or designing to absolute maximum ratings. ? 0.1? bypass capacitor must be connected between pins 1 and 4, and 5 and 8 pin 3 must be left unconnected pin number pin name pin function description 1v dd1 input supply voltage 2v i input data 3 led anode ?must be left unconnected 4 gnd1 input ground 5 gnd2 output ground 6v o output data 7n c not connected 8v dd2 output supply voltage symbol parameter value units t stg storage temperature -55 to +125 ? t opr operating temperature -40 to +100 ? t sol lead solder temperature 260 for 10 sec ? re?w temperature pro?e (refer to relow pro?e) v dd1 input supply voltage 0 to 6.0 v v i input voltage -0.5 to v dd1 + 0.5 v i i input dc current -10 to +10 ma v dd2 output supply voltage 0 to 6.0 v v d output voltage -0.5 to v dd2 + 0.5 v i o av erage output current 10 ma pd1 input power dissipation 90 mw pd2 output power dissipation 70 mw symbol parameter min. max. unit t opr ambient operating temperature -40 +100 ? v dd1 , v dd2 supply voltages 4.5 5.5 v v ih logic high input voltage 2.0 v dd1 v v il logic low input voltage 0 0.8 v t r , t f input signal rise and fall time 1.0 ms
?004 fairchild semiconductor corporation www.fairchildsemi.com fod0721, FOD0720, fod0710 rev. 1.0.8 3 fod0721, FOD0720, fod0710 ?high cmr, 25mbit/sec logic gate optocoupler electrical characteristics (t a = -40? to 100? and 4.5v v dd 5.5v, all typicals are at t a = 25?, v dd = 5v) isolation characteristics (t a = -40? to +100? unless otherwise specied.) *all typicals at t a = 25? notes: 1. device is considered a two terminal device: pins 1, 2, 3 and 4 are shorted together and pins 5, 6, 7 and 8 are shorted together. 2. 3,750 vac rms for 1 minute duration is equivalent to 4,500 vac rms for 1 second duration. symbol parameter test conditions min. typ. max. unit input characteristics i dd1l logic low input supply current v i = 0v 6.5 10.0 ma i dd1h logic high input supply current v i = v dd1 0.8 3.0 ma i dd1 input supply current 13.0 ma i i input current -10 +10 ? output characteristics i dd2l logic low output supply current v i = 0v 5.5 9 ma i dd2h logic high output supply current v i = v dd1 5.3 9 ma v oh logic high output voltage i o = -20?, v i = v ih 4.4 5.0 v v oh i o = -4ma, v i = v ih 4.0 4.8 v v ol logic low output voltage i o = 20?, v i = v il 0 0.1 v v ol i o = 4ma, v i = v il 0.5 1.0 v symbol characteristics test conditions min. typ.* max. unit v iso input-output isolation voltage f = 60hz, t = 1.0 min, i i-o 10? (1)(2) 3750 vac rms r iso isolation resistance v i-o = 500v (1) 10 11 ? c iso isolation capacitance v i-o = 0 , f = 1.0mhz (1) 0.2 pf
?004 fairchild semiconductor corporation www.fairchildsemi.com fod0721, FOD0720, fod0710 rev. 1.0.8 4 fod0721, FOD0720, fod0710 ?high cmr, 25mbit/sec logic gate optocoupler switching characteristics (t a = -40? to 100? and 4.5v v dd 5.5v, all typicals are at t a = 25?, v dd = 5v) notes: 3. t psk is equal to the magnitude of the worst case difference in t phl and/or t plh that will be seen between units at any given temperature within the recommended operating conditions. 4. common mode transient immunity at output high is the maximum tolerable (positive) dvcm/dt on the leading edge of the common mode impulse signal. vcm, to assure that the output will remain high. common mode transient immunity at output low is the maximum tolerable (negative dvcm/dt on the trailing edge of the common pulse signal, vcm, to assure that the output will remain low. symbol parameter test conditions min. typ. max. unit t phl propagation delay time to logic low output c l = 15pf 21 40 ns t plh propagation delay time to logic high output c l = 15pf 23 40 ns pwd pulse width distortion, | t phl ?t plh | fod0710 pw = 80ns, c l = 15pf 2 8 ns FOD0720 pw = 40ns, c l = 15pf 2 8 ns fod0721 pw = 40ns, c l = 15pf 2 6 ns data rate fod0710 12.5 mb/s FOD0720, fod0721 25 mb/s t psk propagation delay skew c l = 15pf (3) 20 ns t r output rise time (10%?0%) 5 ns t f output fall time (90%?0%) 4.5 ns |cm h | common mode transient immunity at output high v i = v dd1 , v o > 0.8 v dd2 v cm = 1000v (4) 20 40 kv/? |cm l | common mode transient immunity at output low v i = 0v, v o < 0.8, v cm = 1000v (4) 20 40 kv/?
?004 fairchild semiconductor corporation www.fairchildsemi.com fod0721, FOD0720, fod0710 rev. 1.0.8 5 fod0721, FOD0720, fod0710 ?high cmr, 25mbit/sec logic gate optocoupler typical performance curves figure 1. typical output voltage vs. input voltage figure 3. typical propogation delay vs. ambient temperature (fod0710) figure 4. typical pulse width distortion vs. ambient temperature (fod0710) figure 5. typical propogation delay vs. ambient temperature (fod0721/FOD0720) figure 6. typical pulse width distortion vs. ambient temperature (fod0721/FOD0720) figure 2. typical input voltage switching threshold vs. input supply voltage 0 1 2 3 4 5 012345 v o -o utput voltage (v) v i -inp ut voltage (v) 1.4 1.5 1.6 1.7 1.8 1.9 4.50 4.75 5.00 5.25 5.50 v ith -t yp ic al input voltage switching threshold (v) v dd1 -i n put supply voltage (v) v dd2 =5.0v -4 0 -20 0 20 4 06080100 t p -pr opagation delay (ns) t a -a mbient temperature ( c) -4 0 -20 0 20 4 06080100 pwd - pulse width distortion (ns) t a -a mb i ent temperature ( c) fr equency = 6.25mhz dut y c ycle = 50% v dd1 =v dd2 =5.0v 18 20 22 24 26 28 -40 -20 0 20 4 06080100 t p -pr opagation delay (ns) t a -a mbient temperature ( c) t phl t plh fr equency = 12.5mhz duty cycle = 50% v dd1 =v dd2 =5.0v -40 -20 0 20 4 06080100 pwd - pulse width distortion (ns) t a -a mbient temperature ( c) fr equency = 12.5mhz duty cycle = 50% v dd1 =v dd 2 =5.0v 18 19 20 21 22 23 24 25 26 t plh t phl -3 -2 -1 0 1 2 3 4 -3 -2 -1 0 1 2 3 4 5
?004 fairchild semiconductor corporation www.fairchildsemi.com fod0721, FOD0720, fod0710 rev. 1.0.8 6 fod0721, FOD0720, fod0710 ?high cmr, 25mbit/sec logic gate optocoupler typical performance curves (continued) figure 7. typical rise and fall time vs. ambient temperature figure 8. typical propogation delay vs. output load capacitance (fod0710) figure 9. typical pulse width distortion vs. output load capacitance (fod0710) figure 10. typical propogation delay vs. output load capacitance (fod0721/FOD0720) figure 11. typical pulse width distortion vs. output load capacitance (fod0721/FOD0720) 6.00 5.50 5.00 4.50 4.00 3.50 3.00 -40 -20 0 20 4 06080100 t r , t f - rise, fall time t a -a mbient temperature ( c) fr equency = 6.25mhz du ty cy cle = 50% v t r dd1 =v dd2 =5.0v 21 22 23 24 25 26 27 28 15 20 25 30 35 40 45 50 55 t p -p ro p agation delay (ns) c l -o utput load capacitance (pf) t plh t phl fr equency = 6.25mhz duty cycle = 50% v dd 1 =v dd2 =5.0v 0.6 0.8 1.0 1.2 1.4 1.6 15 20 25 30 35 40 45 50 55 pwd - pulse width distortion (ns) c l -o utput load capacitance (pf) fr equency = 6.25mhz duty cycle = 50% v dd1 =v dd 2 =5.0v 21 22 23 24 25 26 27 15 20 25 30 35 40 45 50 55 t p -p r opagation delay (ns) c l -o utput load capacitance (pf) fr eq uency = 12.5mhz duty cy cle = 50% v dd1 =v dd2 =5.0v t plh t phl 0.8 0.9 1.0 1.1 1.2 1.3 1.4 15 20 25 30 35 40 45 50 55 pwd - pulse w idth distor tion (ns) c l -o utput load capacitance (pf) fr equency = 12.5mhz duty cycle = 50% v dd 1 =v dd 2 =5.0v t f figure 12. typical rise and fall time vs. output load capacitance (fod0710) 12 10 8 6 4 2 15 20 25 30 35 40 45 50 55 c l -o utput load capacitance (pf) fr equency = 6.25mhz dut y cy cle = 50% v dd1 =v dd2 =5.0v t r , t f - rise, fall time t r t f
?004 fairchild semiconductor corporation www.fairchildsemi.com fod0721, FOD0720, fod0710 rev. 1.0.8 7 fod0721, FOD0720, fod0710 ?high cmr, 25mbit/sec logic gate optocoupler typical performance curves (continued) figure 13. typical rise and fall time vs. output load capacitance (fod0721/FOD0720) figure 14. typical input supply current vs. frequency figure 15. typical output supply current vs. frequency 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 0 2000 4000 6000 8000 10000 12000 i dd1 -i nput supply current (ma) f- fr equency (khz) t a = 100 c t a =25 c t a =-40 c v dd1 =5.5v 5.0 5.2 5.4 5.6 5.8 6.0 0 2000 4000 6000 8000 10000 12000 i dd2 -outputs upply current (ma) f- fr equency (khz) v dd1 =v dd2 =5.5v *pi n6float ing t a = 100 c t a =25 c t a =-40 c 12 10 8 6 4 2 15 20 25 30 35 40 45 50 55 c l -o utput load capacitance (pf) fr equency = 12.5mhz dut y cy cle = 50% v dd1 =v dd2 =5.0v t r , t f - rise, fall time t r t f
?004 fairchild semiconductor corporation www.fairchildsemi.com fod0721, FOD0720, fod0710 rev. 1.0.8 8 fod0721, FOD0720, fod0710 ?high cmr, 25mbit/sec logic gate optocoupler small outline package dimensions note: all dimensions are in millimeters. pa c kage drawings are provided as a service to customers considering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawing and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package speci?ations do not expand the terms of fairchilds worldwide terms and conditions, speci?ally the warranty therein, which covers fairchild products. always visit fairchild semiconductors online packaging area for the most recent package drawings: http://www .f airchildsemi.com/pac kaging/ 0.024 (0.61) 0.050 (1.27) 0.155 (3.94) 0.275 (6.99) 0.060 (1.52) lead coplanarity : 0.004 (0.10) max 0.202 (5.13) 0.182 (4.63) 0.021 (0.53) 0.011 (0.28) 0.050 (1.27) typ 0.244 (6.19) 0.224 (5.69) 0.143 (3.63) 0.123 (3.13) 0.008 (0.20) 0.003 (0.08) 0.010 (0.25) 0.006 (0.16) seating plane 0.164 (4.16) 0.144 (3.66)
?004 fairchild semiconductor corporation www.fairchildsemi.com fod0721, FOD0720, fod0710 rev. 1.0.8 9 fod0721, FOD0720, fod0710 ?high cmr, 25mbit/sec logic gate optocoupler ordering information all packages are lead free per jedec: j-std-020b standard. marking information option order entry identi?r description no suf? fod0721 shipped in tubes (50 units per tube) r2 fod0721r2 tape and reel (2500 units per reel) 1 2 5 3 4 de?itions 1f airchild logo 2d e vice number 3 one digit year code, e.g., ? 4t wo digit work week ranging from ?1 to ?3 5 assembly package code 721 s1 yy x
?004 fairchild semiconductor corporation www.fairchildsemi.com fod0721, FOD0720, fod0710 rev. 1.0.8 10 fod0721, FOD0720, fod0710 ?high cmr, 25mbit/sec logic gate optocoupler carrier tape specification note: all dimensions are in millimeters. reflow profile 4.0 0.10 1.5 min user direction of feed 2.0 0.05 1.75 0.10 5.5 0.05 12.0 0.3 8.0 0.10 0.30 max 8.3 0.10 3.50 0.20 0.1 max 6.40 0.20 5.20 0.20 1.5 0.1/-0 300 280 260 240 220 200 180 160 140 120 100 80 60 40 20 0 temperature ( c) time (s) 0 60 180 120 270 260 c >245 c = 42 sec time above 183 c = 90 sec 360 1.822 c/sec ramp up rate 33 sec
?004 fairchild semiconductor corporation www.fairchildsemi.com fod0721, FOD0720, fod0710 rev. 1.0.8 11 fod0721, FOD0720, fod0710 ?high cmr, 25mbit/sec logic gate optocoupler figure 16. test circuit for propogation delay time and rise time, fall time figure 17. test circuit for instantaneous common mode rejection voltage v in t plh t r v out v ol 50% 90% 10% input output 5v 2.5v v oh t f t phl 1 2 v dd2 = 5v v o 0.1 f 0v?v c l 3 4 8 7 6 5 0.1 f v dd1 = 5v pulse width = 40ns duty cycle = 50% 1 2 v dd2 = 5v v o v cm + 0.1 f sw b a c l 3 4 8 7 6 5 0.1 f v dd1 = 5v v oh 0.8 x v dd switching pos. (a) v in = 5v switching pos. (b) v in = 0v gnd 1kv v ol v cm cm h cm l 0.8v
?004 fairchild semiconductor corporation www.fairchildsemi.com fod0721, FOD0720, fod0710 rev. 1.0.8 12 tradem arks th e following includes registered and unregistered trademarks and service marks, owned by fairchild semiconductor and/or its global subsidiaries ,and is not in tended to be an exhaustive list of all such trademarks. auto-spm build it now coreplus corepower crossvolt ctl current transfer logic ecospark e fficentmax ezswitch* * fair child fairchild semiconductor fa ct quiet series fact f ast fa stvcore fetbench flashwriter * fps f-pfs frfet global power resource sm green fps green fps e-series g max gto in tellimax isoplanar me gabuck mi crocoupler microfet mi cropak m illerdrive moti onmax mo tion-spm optologic op toplanar pdp spm powe r-spm po we rtrench powerxs pr ogrammable active droop qfet qs quiet series r apidconfigure saving our world, 1mw/w/kw at a time sm artmax smart start spm stealth s uperfet sup ersot -3 s upersot -6 s upersot -8 s upremos syncfet sy nc-lock * th ep ower franchise ti nyboost tinybuck ti nylogic tinyopto tinypower tinypwm tinywire trifault detect t ruecurrent * serdes uhc ultra frfet unifet vcx vi sualmax xs *t rademarks of system general corporation, used under license by fairchild semiconductor. disclaimer fa i rchild semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function, or design. fairchild does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. these specifications do not expand the terms of fairchild? worldwide terms and conditions, specifically the warranty therein, which covers t hese products. li fe support policy fa i rchild? products are not authorized for use as critical components in life support devices or systems without the express written approval of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are in tended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance wi th instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. a critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. an ti -counterfeiting policy fairchild semiconductor corporation's anti-counterfeiting policy. fairchild's anti-counterfeiting policy is also stated on our external websi te, www.fairchildsemi.com, under sales support. c ounterfeiting of semiconductor parts is a growing problem in the industry. all manufacturers of semiconductor products are experiencing counterf eiting of their parts. cu stomers who inadvertently purchase counterfeit parts experience many problems such as loss of brand reputation, substandard performance, faile da pplications, and increased cost of production and manufacturing delays. fairchild is taking strong measures to protect ourselves and our customers from the proli feration of counterfeit parts. fairchild strongly encourages customers to purchase fairchild parts either directly from fairchild or from authorized fairchi ld dist ributors who are lis ted by country on our web page cited above. products customers buy either from fairchild directly or from authorized fairchild distributors are ge nuine parts, have full traceability, meet fairchild's quality standards for handling and storage and provide access to fairchild's full range of up-to-date technica land product information. fairchild and our authorized distributors will stand behind all warranties and will appropriately address any warranty issues that may arise. fairc hild will not provide any warranty coverage or other assistance for parts bought from unauthorized sources. fairchild is committed to combat this global problem and encou rage our customers to do their part in stopping this practice by buying direct or from authorized distributors. product status definitions defi nition of terms da tasheet identification product st atus definition ad vance information formative / in design datasheet contains the design specifi cations for product development. s pecifications may change in any manner without notice. pr eliminary datasheet contains preliminary data; supplementary data will be published at a later date. fairchild se mi conductor reserves the right to make changes at any time without notice to improve design. no i dentification needed full production datasheet contains final specifications. fairchi ld semiconductor reserves the right to make changes at any time without notice to improve the design. obsolete not in production datasheet contains specifications on a product that is discontinued by fairchild semiconductor. th e datasheet is for reference information only. rev. i40 first production fod0721, FOD0720, fod0710 ?high cmr, 25mbit/sec logic gate optocoupler

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